HM534253B Series
I/O0 – I/O3 (input/output pins):
I/O pins function as mask data at the falling edge of
RAS
(in mask write
mode). Data is written only to high I/O pins. Data on low I/O pins are masked and internal data are retained.
After that, they function as input/output pins as those of a standard DRAM. In block write cycle, they
function as address mask data at the falling edges of
CAS.
EO
6
DT/OE
(input pin):
D T/OE
pin functions as
DT
(data transfer) pin at the falling edge of
RAS
and as
OE
(output enable) pin after that. When
DT
is low at the falling edge of
RAS,
this cycle becomes a transfer cycle.
When
DT
is high at the falling edge of
RAS,
RAM and SAM operate independently.
SC (input pin):
SC is a basic SAM clock. In a serial read cycle, data outputs from an SI/O pin
synchronously with the rising edge of SC. In a serial write cycle, data on an SI/O pin at the rising edge of SC
is fetched into the SAM data register.
SE(input
pin):
SE
pin activates SAM. When
SE
is high, SI/O is in the high impedance state in serial read
cycle and data on SI/O is not fetched into the SAM data register in serial write cycle.
SE
can be used as a
mask for serial write because internal pointer is incremented at the rising edge of SC.
SI/O0 – SI/O3 (input/output pins):
SI/Os are input/output pins in SAM. Direction of input/output is
determined by the previous transfer cycle. When it was a read transfer cycle, SI/O outputs data. When it was
a pseudo transfer cycle or write transfer cycle, SI/O inputs data.
DSF (input pin):
DSF is a special function data input flag pin. It is set to high at the falling edge of
RAS
when new functions such as color register read/write, split transfer, and flash write, are used. DSF is set to
high at the falling edge of
CAS
when block write is executed.
QSF (output pin):
QSF outputs data of address A8 in SAM. QSF is switched from low to high by accessing
address 255 in SAM and from high to low by accessing 511 address in SAM.
LP
Data Sheet E0165H10
ro
du
ct
ELPIDA [ ELPIDA MEMORY ]
