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HM534253BJ-8 参数 Datasheet PDF下载

HM534253BJ-8图片预览
型号: HM534253BJ-8
PDF下载: 下载PDF文件 查看货源
内容描述: 1M的VRAM ( 256千字×4位) [1 M VRAM (256-kword x 4-bit)]
分类和应用: 存储内存集成电路
文件页数/大小: 45 页 / 448 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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HM534253B Series
High-Speed Page Mode Cycle
(DT/OE high,
CAS
high and DSF low at the falling edge of
RAS)
High-speed page mode cycle reads/writes the data of the same row address at high speed by toggling
CAS
while
RAS
is low. Its cycle time is one third of the random read/write cycle. In this cycle, read, write, and
block write cycles can be mixed. Note that address access time (t
AA
),
RAS
to column address delay time
(t
RAD
), and access time from
CAS
precharge (t
ACP
) are added. In one
RAS
cycle, 512-word memory cells of the
same row address can be accessed. It is necessary to specify access frequency within t
RASP
max (100 µs).
Color Register Set/Read Cycle
(CAS high,
DT/OE
high,
WE
high and DSF high at the falling edge of
RAS)
In color register set cycle, color data is set to the internal color register used in flash write cycle or block write
cycle. 4 bits of internal color register are provided at each I/O. This register is composed of static circuits, so
once it is set, it retains the data until reset. Color register set cycle is just as same as the usual write cycle
except that DSF is set high at the falling edge of
RAS,
and read, early write and delayed write cycle can be
executed. In this cycle, the HM534253B refreshes the row address fetched at the falling edge of
RAS.
Flash Write Cycle
(CAS high,
DT/OE
high,
WE
low, and DSF high at the falling edge of
RAS)
In a flash write cycle, a row of data (512-word
×
4-bit) is cleared to 0 or 1 at each I/O according to the data of
color register mentioned before. It is also necessary to mask I/O in this cycle. When
CAS
and
DT/OE
are set
high,
WE
is low, and DSF is high at the falling edge of
RAS,
this cycle starts. Then, the row address to clear
is given to row address and mask data is given to I/O. Mask data is as same as that of a RAM write cycle.
High I/O is cleared, low I/O is not cleared and the internal data is retained. Cycle time is the same as those of
RAM read/write cycles, so all bits can be cleared in 1/512 of the usual cycle time. (See figure 1.)
EO
8
LP
Data Sheet E0165H10
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