HM538253B/HM538254B Series
Pin Functions
RAS (input pin): RAS is a basic RAM signal. It is active in low level and standby in high level. Row address
and signals as shown in table 1 are input at the falling edge of RAS. The input level of these signals
determines the operation cycle of the HM538253B/HM538254B.
CAS (input pin): Column address and DSF1 signals are fetched into the chip at the falling edge of CAS,
which determines the operation mode of the HM538253B/HM538254B.
A0–A8 (input pins): Row address (AX0–AX8) is determined by A0–A8 level at the falling edge of RAS.
Column address (AY0–AY8) is determined by A0–A8 level at the falling edge of CAS. In transfer cycles,
row address is the address on the word line which transfers data with the SAM data register, and column
address is the SAM start address after transfer.
WE: The WE pin has two functions at the falling edge of RAS and after. When WE is low at the falling edge
of RAS, the HM538253B/ HM538254B turns to mask write mode. According to the I/O level at the time,
write on each I/O can be masked. (WE level at the falling edge of RAS is don’t care in read cycle.) When
WE is high at the falling edge of RAS, no mask write cycle is executed. After that, WE switches to read/write
cycles. In a transfer cycle, the direction of transfer is determined by WE level at the falling edge of RAS.
When WE is low, data is transferred from SAM to RAM (data is written into RAM), and when WE is high,
data is transferred from RAM to SAM (data is read from RAM).
I/O0–I/O7 (input/output pins): I/O pins function as mask data at the falling edge of RAS (in mask write
mode). Data is written only to high I/O pins. Data on low I/O pins is masked and internal data is retained.
After that, they function as input/output pins as those of a standard DRAM. In block write cycle, the data
functions as column mask data at the falling edges of CAS and WE.
DT/OE (input pin): The DT/OE pin functions as a DT (data transfer) pin at the falling edge of RAS and as
an OE (output enable) pin after that. When DT is low at the falling edge of RAS, this cycle becomes a transfer
cycle. When DT is high at the falling edge of RAS, RAM and SAM operate independently.
SC (input pin): SC is a basic SAM clock. In a serial read cycle, data outputs from an SI/O pin synchronously
with the rising edge of SC. In a serial write cycle, data on an SI/O pin at the rising edge of SC is fetched into
the SAM data register.
SE (input pin): SE pin activates SAM. When SE is high, SI/O is in the high impedance state in serial read
cycle and data on SI/O is not fetched into the SAM data register in serial write cycle. SE can be used as a
mask for serial write because the internal pointer is incremented at the rising edge of SC.
SI/O0–SI/O7 (input/output pins): SI/Os are SAM input/output pins. I/O direction is determined by the
previous transfer cycle. If it was a read transfer cycle, SI/O outputs data. If it was a masked write transfer
cycle, SI/O inputs data.
DSF1 (input pin): DSF1 is a special function data input flag pin. It is set to high at the falling edge of RAS
when new functions such as color register and mask register read/write, split transfer, and flash write, are
used.
Data Sheet E0163H10
6
ELPIDA [ ELPIDA MEMORY ]
