HM538253B/HM538254B Series
Table 1
Operation Cycles of the HM538253B/HM538254B (cont)
Register
Mnemonic
Code
Write Pers
Mask W.M.
No. Of
Bndry Function
WM
Color
—
CBRS
CBRR
CBRN
MWT
—
—
—
Set
CBR refresh with stop register set
—
Reset Reset
—
Reset CBR refresh with register reset
—
—
—
—
—
—
CBR refresh (no reset)
Yes
No
Load/use
Use
—
Masked write transfer (new/old mask)
Yes
MSWT
Yes
No
Yes
Load/use
Use
—
Use
Masked split write transfer (new/old mask)
RT
—
—
—
—
—
—
—
—
—
Read transfer
SRT
RWM
—
Use
—
Split read transfer
Read/write (new/old mask)
Yes
No
Yes
Load/use
Use
BWM
Yes
No
Yes
Load/use
Use
—
Block write (new/old mask)
RW (no)
BW (no)
FWM
No
No
No
—
—
—
—
—
—
Read/write (no mask)
No
Use
Block write (no mask)
Yes
No
Yes
Load/use Use
Use
Masked flash write (new/old mask)
LMR and
Old Mask Set
—
Set
Load
—
—
Load mask register and old mask set
Load color resister set
LCR
—
—
—
—
—
—
Load
—
—
—
Option
Notes: 1. With CBRS, all SAM operations use stop register.
2. After LMR, RWM, BWM, FWM, MWT, and MSWT, use old mask which can be reset by CBRR
3. DSF2 is fixed low in all operation (for the addition of operation modes in future).
Operation of HM538253B/HM538254B
RAM Port Operation
RAM Read Cycle (DT/OE high, CAS high and DSF1 low at the falling edge of RAS, DSF1 low at the falling
edge of CAS: Mnemonic Code; R) Row address is entered at the RAS falling edge and column address at the
CAS falling edge to the device as in standard DRAM operation. Then, when WE is high and DT/OE is low
while CAS is low, the selected address data outputs through the I/O pin. At the falling edge of RAS, DT/OE
and CAS become high to distinguish RAM read cycle from transfer cycle and CBR refresh cycle. Address
access time (tAA) and RAS to column address delay time (tRAD) specifications are added to enable fast page
mode/hyper page mode.
Data Sheet E0163H10
8
ELPIDA [ ELPIDA MEMORY ]
