EM39LV040
4M (512Kx8) Bits Flash Memory
SPECIFICATION
Timing Diagrams
Read Cycle Timing Diagram
T
RC
A18~A0
CE#
T
CE
T
AA
OE#
T
OE
T
OHZ
V
IH
WE#
T
OLZ
T
CLZ
T
OH
Data Valid
T
CHZ
Data Valid
HIGH-Z
HIGH-Z
DQ7-0
Figure 1:
Read Cycle Timing Diagram
WE# Controlled Program Cycle Timing Diagram
Internal Program Operation Starts
T
BP
A18~A0
5555
T
AH
WE#
T
WP
T
WPH
T
AS
OE#
T
DS
2AAA
5555
ADDR
T
DH
T
CH
CE#
T
CS
DQ7-0
AA
SW0
55
SW1
A0
SW2
DATA
Byte
(ADDR/DATA)
Figure 2:
WE# Controlled Program Cycle Timing Diagram
This specification is subject to change without further notice. (07.22.2004 V1.0)
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