EM39LV040
4M (512Kx8) Bits Flash Memory
SPECIFICATION
Toggle Bit Timing Diagram
A18~A0
T
CE
CE#
T
OEH
OE#
WE#
DQ6
Two Read Cycles
With Same Outputs
T
OE
T
OES
Figure 5:
Toggle Bit Timing Diagram
WE# Controlled Chip-Erase Timing Diagram
Six-Byte Code For Chip-Erase
T
SCE
5555
A18~A0
CE#
OE#
5555
2AAA
5555
5555
2AAA
T
WP
WE#
AA
SW0
55
SW1
80
SW2
AA
SW3
55
SW4
10
SW5
DQ7-0
Note:
This device also supports CE# controlled Chip-Erase operation. The WE#and CE#
signals are interchageable as long as minimum timings are met. (See Table 10)
Figure 6:
WE# Controlled Chip-Erase Timing Diagram
This specification is subject to change without further notice. (07.22.2004 V1.0)
Page 13 of 21
EMC [ ELAN MICROELECTRONICS CORP ]
