EM78452
8-Bit Microcontroller
5.3 TCC/WDT Presacler
An 8-bit counter is available as prescaler for the TCC or WDT. The prescaler is
available for either the TCC or WDT at any given time, and the PAB bit of CONT
register is used to determine the prescaler assignment. The PSR0~PSR2 bits
determine the prescaler ratio. The prescaler is cleared each time the instruction is
written to TCC in TCC mode. The WDT and prescaler, when assigned to WDT mode,
are cleared by the WDTC or SLEP instructions. Fig. 5-5 depicts the circuit diagram of
TCC/WDT.
R1 (TCC) is an 8-bit timer/counter. TCC will increase by one at every instruction
cycle (without prescaler).
The watchdog timer is a free running on-chip RC oscillator. The WDT will keep
running even when the oscillator driver has been turned off (i.e. in sleep mode).
During normal or sleep mode operation, a WDT time-out (if enabled) will cause the
device to reset. The WDT can be enabled or disabled any time during normal
mode by software programming (if Code Option bit ENWDT is "1"). Refer to the
WDTE bit of the IOCE register. Without presacler, the WDT time-out period is
approximately 18 ms
.
5.4 I/O Ports
The I/O registers, from Port 5 to Port 9, are bidirectional tri-state I/O ports. P60~P67,
P74~P75, and P90~P91 provides internal pull-high. P60~P67, P74~P75, and
P90~P95 provides programmable wake-up function through software. P76~P77 can
have an open-drain output by software control. P80~P81 are the R-option pins which
are enabled by software. When the R-option function is used, it is recommended that
P80 and P81 be used as output pins. During R-option enabled state, P80 and P81
must be programmed as input pins. If an external resistor is connected to P80 (P81) for
the R-option function, the current consumption should be taken as an important factor
in the applications for low power consideration.
The I/O ports can be defined as "input" or "output" pins by the I/O control registers
(IOC5~IOC9) under program control. The I/O registers and I/O control registers are
both readable and writable. The I/O interface circuit is shown in Fig. 5-6. Note that the
reading path source of input and output pins is different when reading the I/O port.
1
Vdd = 5V, set up time period = 16.2ms ± 30%
Vdd = 3V, set up time period = 18.0ms ± 30%
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
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EMC [ ELAN MICROELECTRONICS CORP ]
