EM78452
8-Bit Microcontroller
The SSE bit will be kept in “1“ if the communication is still undergoing. This flag must
be cleared as the shifting is completed. Users can determine if the next write attempt is
available.
SBRS2~SBRS0: Programming the clock frequency/rates and sources.
Clock Select:Selects either the internal or the external clock as the shifting clock.
Edge Select: Selects the appropriate clock edges by programming the CES bit
5.5.3 SPI Signal & Pin Description
The detailed functions of the four pins, SDI, SDO, SCK, and /SS, which are shown in
Fig. 5-8.
SRDY/P92 (Pin 6):
Slave ready pin
In Slave mode when code option bit 7 (SPIHSK) set to 0, P91 (SRDY) this pin will
be set to high after SPI enable and SSE bit set to 1.
SDI/P92 (Pin 7):
Serial Data In,
Receive sequentially, the Most Significant Bit (MSB) first, Least Significant Bit
(LSB) last,
Defined as high-impedance, if not selected,
Program the same clock rate and clock edge to latch on both the master and slave
devices,
The byte received will update the transmitted byte,
Both the RBF and RBFIF bits (located in Register 0x0C) will be set as the SPI
operation is completed.
Timing is shown in Fig. 5-12 and 5-13.
SDO/P93 (Pin 8):
Serial Data Out,
Transmit sequentially; the Most Significant Bit (MSB) first, Least Significant Bit
(LSB) last,
Program the same clock rate and clock edge to latch on both the master and slave
devices,
The received byte will update the transmitted byte,
The CES (located in Register 0x0D) bit will be reset, as the SPI operation is
completed.
Timing is shown in Fig. 5-12 and 5-13.
Product Specification (V1.0) 10.18.2007
(This specification is subject to change without further notice)
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EMC [ ELAN MICROELECTRONICS CORP ]
