ePVP6800
VFD Controller
PS0~PS3 in the status register (R5 PAGE 1) upon execution of a "JMP,” "CALL,” "ADD R2, A.” or
"MOV R2, A'' instruction.
If an interrupt is triggered, PROGRAM ROM will jump to address 0x08 at Page0. The CPU will
automatically store ACC, R3 status, and R5 PAGE 1, and they will be restored after execution of
instruction RETI.
7.2.4 R3 (Status, Page Selection)
(Status Flag, Page Selection Bits)
Bit 7
RPAGE1
R/W-0
R/W-0
Bit 6
Bit 5
Bit 4
T
R
R
Bit 3
P
R
R
Bit 2
Z
R/W
R/W
Bit 1
DC
R/W
R/W
Bit 0
C
R/W
R/W
RPAGE0
IOCPAGE
R/W-0
R/W-0
R/W-0
R/W-0
Bit 0 (C) : Carry flag
The carry flag is affected by following operation :
a. Addition : CF as a carry out indicator, when the addition operation has a carry-out, CF will
be "1", in
another word, if the operation has no carry-out, CF will be "0".
b. Subtraction : CF as a borrow-in indicator, when the subtraction operation must has a
borrow-in, the CF
will be "0", in another word, if no borrow-in, CF will be "1".
c. Comparision : CF is as a borrow-in indicator for Comparision operation as the same as
subtraction
operation.
d. Rotation : CF shifts into the empty bit of accumulator for the rotation and holds the shift out
data after
rotation.
Bit 1 (DC) : Auxiliary carry flag
Bit 2 (Z) :
Zero flag
ZF is affected by the result of ALU, if the ALU operation generate a "0" result, the ZF will be
"1", otherwise, the ZF will be "0".
Bit 3 (P)
:
Bit 4 (T)
:
Power down bit
Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command.
Time-out bit
Set to 1 by the "SLEP" and "WDTC" command, or during power up and reset to 0 by WDT
timeout.
Event
WDT wake up from sleep mode
WDT time out (not sleep mode)
/RESET wake up from sleep
Power up
Low pulse on /RESET
8 of 47
11. 28.2004 (V1.23)
T
0
0
1
1
x
P
0
1
0
1
X
Remarks
x
:
don't care
This specification is subject to change without further notice.
EMC [ ELAN MICROELECTRONICS CORP ]
