ePVP6800
VFD Controller
7.2.5 R4 (RAM Selection For Common Registers R20 ~ R3F))
(RAM Selection Register)
Bit 7
RB1
R/W-0
Bit 6
RB0
R/W-0
Bit 5
RSR5
R/W
Bit 4
RSR4
R/W
Bit 3
RSR3
R/W
Bit 2
RSR2
R/W
Bit 1
RSR1
R/W
Bit 0
RSR0
R/W
Bit 0 ~ Bit 5 (RSR0 ~ RSR5)
:
Indirect address for common Registers R20 ~ R3F.
RSR bits are used to select up to 32 registers (R20 to R3F) in the
indirect address mode.
Bit 6 ~ Bit 7 (RB0 ~ RB1)
:
Bank selection bits for common Registers R20 ~ R3F.
These selection bits are used to determine which bank is activated
among the 4 banks for 32 register (R20 to R3F).
Refer to Section 7.1
Operation Registers Configuration
for details.
7.2.6 R5 (PORT5 Output Data, Program Page Selection)
a) PAGE 0 (PORT5 Output Data Register for HV or
General Purpose Input pins:
p54~p57)
Bit 7
P57
W-0
Bit 6
P56
W-0
Bit 5
P55
W-0
Bit 4
P54
W-0
Bit 3
-
-
Bit 2
-
-
Bit 1
-
-
Bit 0
-
-
b) PAGE 1 (Program ROM Page Register)
Bit 7
-
-
Bit 6
-
-
Bit 5
-
-
Bit 4
-
-
Bit 3
-
-
Bit 2
-
-
Bit 1
PS1
R/W-0
Bit 0
PS0
R/W-0
Bit 0 ~ Bit 3 (PS0 ~ PS3)
:
Program page selection bits
PS1 PS0
0
0
0
1
Program Memory
Page (Address)
Page 0
Page 1
PAGE instruction is used to select the program page to be accessed. The selected program page is
maintained by Elan compiler. PAGE instruction will change your program by inserting the instruction
within program.
10 of 47
11. 28.2004 (V1.23)
This specification is subject to change without further notice.
EMC [ ELAN MICROELECTRONICS CORP ]
