EM620FU16B Series
Low Power, 128Kx16 SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 CONTROLLED)
t
WC
Address
t
(2)
t
(4)
CW1,2
WR
CS1
CS2
t
(3)
AS
t
AW
t
BW
UB,LB
WE
t
(1)
t
(3)
WP
AS
t
DH
t
DW
Data in
Data Valid
High-Z
High-Z
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS1, a high CS2 and low WE. A write begins at the latest
transition among CS1 goes low, CS2 goes high and WE goes low. A write ends at the earliest transition
among CS1 goes low, CS2 goes high and WE goes high. The tWP is measured from the beginning of write
to the end of write.
2. tCW is measured from the CS1 going low CS2 going high to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS1
or WE going high or CS2 going low.
8
EMLSI [ Emerging Memory & Logic Solutions Inc ]
