EM620FU16B Series
Low Power, 128Kx16 SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1). (Address Controlled, CS1=OE=V , CS2=WE=V )
IL
IH
t
RC
Address
Data Out
t
AA
t
OH
Previous Data Valid
Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE = V )
IH
t
RC
Address
t
AA
t
OH
t
CO1,2
CS1
CS2
t
HZ1,2
t
t
BA
OE
UB,LB
t
t
BHZ
OHZ
OE
t
OLZ
High-Z
Data Out
Data Valid
t
BLZ
t
LZ1,2
NOTES (READ CYCLE)
1. tHZ1,2 and tOHZ are defined as the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
2. At any given temperature and voltage condition, tHZ1,2(Max.) is less than tLZ1,2(Min.) both for a given device and from device to
device interconnection.
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