EM625FU8E-55LF 参数 Datasheet PDF下载

EM620FV8BT Series

Low Power, 256Kx8 SRAM

TIMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=V

IL

, CS2=WE=V

IH

)

t

RC

Address

t

AA

t

OH

Data Out

Previous Data Valid

Data Valid

TIMING WAVEFORM OF READ CYCLE(2) (WE = V

IH

)

t

RC

Address

t

AA

CS1

t

CO1,2

t

OH

CS2

t

OE

OE

t

OLZ

Data Valid

t

HZ1,2

t

OHZ

t

WHZ

Data Out

High-Z

t

LZ1,2

NOTES

(READ CYCLE)

1. t

HZ1,2

and t

OHZ

are defined as the outputs achieve the open circuit conditions and are not referenced to output voltage levels.

2. At any given temperature and voltage condition, t

HZ1,2

(Max.) is less than t

LZ1,2

(Min.) both for a given device and from device to

device interconnection.

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