EM641FT8
Low Power, 512Kx8 SRAM
AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference)
3)
VTM
Input Pulse Level : 0V to VCC
Input Rise and Fall Time : 1V/ns
Input and Output reference Voltage : 0.5VCC
Output Load (See right) : CL1) = 100pF + 1 TTL (70ns)
2)
R1
Output
CL1) = 30pF + 1 TTL (45ns/55ns)
Notes :
2)
CL1)
R2
1. Including scope and Jig capacitance
2. R1 = 1800 ohm,
3. VTM VCC
4. CL = 5pF + 1 TTL (measurement with tLZ, tOLZ, tHZ, tOHZ, tWHZ)
R2 = 990 ohm
=
o
o
READ CYCLE (V = 4.5V to 5.5V, GND = 0V, T = -40 C to +85 C)
cc
A
45ns
Max
55ns
Max
70ns
Max
Symbol
Parameter
Unit
Min
Min
Min
Read cycle time
tRC
tAA
45
-
55
-
70
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
-
-
45
45
25
-
-
-
55
55
30
-
-
-
70
70
35
-
Chip select to output
tCO
tOE
tLZ
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
-
-
-
10
5
10
5
10
5
tOLZ
tHZ
tOHZ
tOH
-
-
-
0
20
15
-
0
20
20
-
0
25
25
-
0
0
0
10
10
10
o
o
WRITE CYCLE (V = 4.5V to 5.5V, GND = 0V, T = -40 C to +85 C)
cc
Parameter
Write cycle time
A
45ns
55ns
Max
70ns
Unit
Symbol
Min
Max
Min
Min
Max
tWC
tCW
tAS
45
-
-
55
-
-
70
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip select to end of write
Address setup time
45
0
45
0
60
0
-
-
-
-
Address valid to end of write
Write pulse width
tAW
tWP
tWR
tWHZ
tDW
tDH
45
35
0
-
45
40
0
-
60
50
0
-
-
-
-
Write recovery time
-
-
-
Write to ouput high-Z
0
15
0
20
0
20
Data to write time overlap
Data hold from write time
End of write to output low-Z
25
0
25
0
30
0
-
-
-
-
-
-
tOW
5
5
5
5
EMLSI [ Emerging Memory & Logic Solutions Inc ]
