EM641FT8
TIMING WAVEFORM OF WRITE CYCLE(3) (WE Controlled, OE LOW)
Low Power, 512Kx8 SRAM
t
WC
Address
t
CW
CS
t
AW
t
AS
3)
WE
t
DW
Data in
High-Z
t
WHZ
Data out
Data Undefined
Data Valid
2)
t
WR
4)
t
WP
1)
t
DH
High-Z
NOTES
(WRITE CYCLE)
1. A write occurs during the overlap(t
WP
) of low CS and low WE. A write begins at the latest transition among
CS goes low and WE goes low. A write ends at the earliest transition when CS goes high and WE goes high.
The t
WP
is measured from the beginning of write to the end of write.
2. t
CW
is measured from the CS going low to end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end of write to the address change. t
WR
applied in case a write ends as CS
or WE going high.
8
EMLSI [ Emerging Memory & Logic Solutions Inc ]
