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EM6603 参数 Datasheet PDF下载

EM6603图片预览
型号: EM6603
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗多I / O微控制器 [Ultra Low Power Multi I/O Microcontroller]
分类和应用: 微控制器
文件页数/大小: 39 页 / 670 K
品牌: EMMICRO [ EM MICROELECTRONIC - MARIN SA ]
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EM6603
SPECIFICATION change
date
Chapter
Version
(page)
9/11/99 ver.2.2 All
27/6/97 B/151 All
27/6/97 B/151 All
27/6/97 B/151 (1,2)
16.4(30,31)
27/6/97 B/151 (4)
2 (5)
27/6/97 B/151
27/6/97 B/151
27/6/97 B/151
27/6/97 B/151
27/6/97 B/151
27/6/97 B/151
6 (9)
6.4 (11)
6.6 (13)
8 (16)
8 (16)
8.1 (17)
PA3 input terminal
old text
new text
New specifications (paper format only)
B/151 new version in Doc Control
typical 1.8µA active mode
typical 0.35µA standby mode
For Vdd less then 1.4V it is recommended
that Vdd is connected directly to Vreg
For Vdd>1.8V then the configuration
shown in Fig.3 should be used.
Table 10 option register – Option
new table and text describing option
register
below Figure 7. PortB new explanation of
mask options
below Figure 8. PortC new explanation of
mask options
First paragraph changed due to new
counter feature added – PA3 clk source
(debounced or not, Rising/Falling)
PA3 input terminal (see tables 28 and 29)
added in Table 24. Timer clock selection
Table 28 PA3 counter input selection –
PA3cnt
Table 29 PA3 counter input selection
new tables describing PA3cnt register
Figure 10 Timer/Event Counter adapted
new description below Figure 11 Interrupt
Request generation
new formulation and more precise
explanation of SVLD (no functional
change)
Figure 12. Serail write buffer
1024 Hz input added in MUX
New explanation of SWB concerning
length and IRQ
New explanation of SWB in interactive
mode
New explanation of Metal mask options
below Table 40 Input/output Ports
Removed (software controlled)
New register PA3cnt at address 65 hex
VDD_range 1 / +1.4 ..+3.6V
VDD_range 2 (Vreg=VDD) / +1.2 ..+1.8V
VDD_range 1 / +1.4 ..+3.6V
VDD_range 2 (Vreg=VDD) / +1.2 ..+1.8V
New way of specifying
I
OL
= f(V
OL
,Vdd), I
OH
= f(V
OH
,Vdd),
New way of specifying Resistors
[kΩ]
instead with currents
New relative way of specifying SVLD
precision and range for 3 levels
±
x%
Max C
Qin
10.0 pf
Max C
Qout
20.0 pf
03/02 REV. G/439
Version 2.2
New pagination & new table nb.
typical 2.7µA active mode
typical 0.3µA standby mode
27/6/97 B/151
27/6/97 B/151
27/6/97 B/151
27/6/97 B/151
27/6/97 B/151
27/6/97 B/151
27/6/97 B/151
27/6/97 B/151
27/6/97 B/151
27/6/97 B/151
27/6/97 B/151
27/6/97 B/151
27/6/97 B/151
27/6/97 B/151
9.1 (19)
10 (20)
11 (22)
11.1 (23)
11.2 (25)
14 (27)
14 (27)
15 (28)
16.2 (30)
16.2 (30)
16.5 (31)
16.5 (32)
16.6 (32)
16.7 (33)
Table 39 Watchdog metal option
VDD
VDD
V
OL
= f(I
OL
,Vdd),
V
OH
= f(I
OH
,Vdd),
Input Pull-Up/Down resistor
expressed by currents
Absolute SVLD levels
2.50V, 2.00V, 1.25V
Max C
Qin
8.5 pf
Max C
Qout
15.9 pf
Copyright
2002, EM Microelectronic-Marin SA
37
www.emmicroelectronic.com