EN5337QI
Input Under-Voltage Lock-Out
Internal circuits ensure that the converter will
not start switching until the input voltage is
above the specified minimum voltage.
Hysteresis, input de-glitch, and output leading
edge blanking ensure high noise immunity and
prevent false UVLO triggers.
Compensation
The EN5337QI uses a type 3 compensation
network. A piece of the compensation circuit is
the phase lead capacitor C
A
in Figure 5. This
network will provide wide loop bandwidth and
excellent transient performance for most
applications. It is optimized for use with about
50μF of output filter capacitance at the voltage
sensing point. Additional load decoupling
capacitance may be placed beyond the voltage
sensing point outside the control loop. Voltage
mode operation provides high noise immunity
at light load, and low output impedance.
In some applications modifications to the
compensation may be required. For more
information, contact Enpirion Applications
Engineering support.
Application Information
The EN5337QI output voltage is determined by
the voltage presented at the XFB pin. This
voltage is set by way of a resistor divider
between V
OUT
and AGND with the midpoint
going to XFB. A phase lead capacitor C
A
is
also required for stabilizing the loop. Figure 5
shows the required components and the
equations to calculate the values.
V
OUT
R
A
C
A
XFB
R
B
RA
=
150
k
Ω
,
CA
=
22
pF
RB
=
0.75 *
RA
(
VOUT
−
0.75
V
)
some applications, lower value capacitors are
needed in parallel with the larger, capacitors in
order to provide high frequency decoupling.
Recommended Input Capacitors
Description
10uF, 10V, 10%
X7R, 1206
(1-2 capacitors needed)
22uF, 10V, 20%
X5R, 1206
(1 capacitor needed)
MFG
Murata
Taiyo Yuden
Murata
Taiyo Yuden
P/N
GRM31CR71A106KA01L
LMK316B7106KL-T
GRM31CR61A226ME19L
LMK316BJ226ML-T
Output Capacitor Selection
The EN5337QI has been optimized for use
with approximately 50μF of output filter
capacitance at the voltage sensing point
Additional load decoupling capacitance may be
placed beyond the voltage sensing point
outside the control loop. Low ESR ceramic
capacitors are required with X5R or X7R rated
dielectric formulation.
Y5V or equivalent
dielectric formulations must not be used as
these lose too much capacitance with
frequency, temperature and bias voltage.
Output ripple voltage is determined by the
aggregate output capacitor impedance. Output
impedance, denoted as Z, is comprised of
effective series resistance, ESR, and effective
series inductance, ESL:
Z = ESR + ESL
Placing output capacitors in parallel reduces
the impedance and will hence result in lower
9
6/18/2009
Figure 5: V
OUT
Resistor Divider Network and
Compensation Capacitor C
A
Input Capacitor Selection
The EN5337QI requires between 10uF and
20uF of input capacitance. Low-cost, low-ESR
ceramic capacitors should be used as input
capacitors for this converter. The dielectric
must be X5R or X7R rated. Y5V or equivalent
dielectric formulations must not be used as
these lose too much capacitance with
frequency, temperature and bias voltage. In
©Enpirion
2009 all rights reserved, E&OE
02638
www.enpirion.com
Rev:D
ENPIRION [ ENPIRION, INC. ]
