EN6337QI
Typical PWM Ripple Voltages
Output Capacitor
Configuration
1 x 47 µF
47 µF + 10 µF
Typical Output Ripple (mVp-p)
(as measured on EN6337QI
Evaluation Board)*
25
14
device. Additional bulk output capacitance
beyond the above recommendations can be
used on the output node of the EN6337QI as
long as the bulk capacitors are far enough from
the V
OUT
sense point such that they don’t
interfere with the control loop operation.
In some cases modifications to the
compensation or output filter capacitance may
be required to optimize device performance
such as transient response, ripple, or hold-up
time. The EN6337QI provides the capability to
modify the control loop response to allow for
customization for such applications. For more
information, contact Enpirion Applications
Engineering support.
* Note: 20 MHz BW limit
Recommended Output Capacitors
Description
47uF, 6.3V, 20%
X5R, 1206
(1 or 2 capacitors needed)
10uF, 10V, 10%
X5R, 1206
(Optional 1 capacitor in
parallel with 47uF above)
MFG
Murata
Taiyo
Yuden
Murata
Taiyo
Yuden
P/N
GRM31CR60J476ME19L
JMK316BJ476ML-T
GRM31CR71A106KA01L
LMK316BJ226ML-T
For best LLM performance, we recommend
using just 2x47uF capacitors mentioned in the
above table, and no 10uF capacitor.
The V
OUT
sense point should be just after the
last output filter capacitor right next to the
Power-Up Sequencing
During power-up, ENABLE should not be
asserted before PVIN, and PVIN should not be
asserted before AVIN. Tying all three pins
together meets these requirements.
Thermal Considerations
The Enpirion EN6337QI DC-DC converter is
packaged in a 7x4x1.85mm 38-pin QFN
package. The QFN package is constructed
with copper lead frames that have exposed
thermal pads. The recommended maximum
junction temperature for continuous operation
is 125°C. Continuous operation above 125°C
will reduce long-term reliability. The device has
a thermal overload protection circuit designed
to shut it off at a junction temperature specified
in the Electrical Characteristics Table.
The silicon is mounted on a copper thermal
pad that is exposed at the bottom of the
package. The thermal resistance from the
silicon to the exposed thermal pad is very low.
In order to take advantage of this low
resistance, the exposed thermal pad on the
package should be soldered directly on to a
copper ground pad on the printed circuit board
(PCB). The PCB then acts as a heat sink. In
order for the PCB to be an effective heat sink,
the device thermal pad should be coupled to
copper ground planes or special heat sink
structures designed into the PCB (refer to the
Layout Recommendations section).
©Enpirion
2011 all rights reserved, E&OE
05800
The junction temperature, T
J
, is calculated from
the ambient temperature, T
A
, the device power
dissipation, PD, and the device junction-to-
ambient thermal resistance,
θ
JA
in °C/W, as
follows:
T
J
= T
A
+ (P
D
) (θ
JA
)
The junction temperature, T
J
, can also be
expressed in terms of the device case
temperature, T
C
, and the device junction-to-
case thermal resistance,
θ
JC
in °C/W, as
follows:
T
J
= T
C
+ (P
D
) (θ
JC
)
The device case temperature, T
C
, is the
temperature at the center of the exposed
thermal pad at the bottom of the package.
The device junction-to-ambient and junction-to-
case thermal resistances,
θ
JA
and
θ
JC
, are
shown in the Thermal Characteristics table on
page 3. The
θ
JC
is a function of the device and
the QFN package design. The
θ
JA
is a function
of
θ
JC
and the user’s system design
parameters
that
include
the
thermal
effectiveness of the customer PCB and airflow.
13
6/17/2011
www.enpirion.com
Rev:
B
ENPIRION [ ENPIRION, INC. ]
