EN25B05
Table 5. Manufacturer and Device Identification
Boot Type
OP Code
ABh / 90h
EN25B05(Bottom Boot)
9Fh
ABh / 90h
EN25B05T(Top Boot)
9Fh
1Ch
2010h
1Ch
1Ch
2010h
25h
(M7-M0)
1Ch
(ID15-ID0)
(ID7-ID0)
95h
Write Enable (WREN) (06h)
The Write Enable (WREN) instruction (Figure 5) sets the Write Enable Latch (WEL) bit. The Write Enable
Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and
Write Status Register (WRSR) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (CS#) Low, sending the instruction
code, and then driving Chip Select (CS#) High.
Write Disable (WRDI) (04h)
The Write Disable instruction (Figure 6) resets the Write Enable Latch (WEL) bit in the Status Register to
a 0. The Write Disable instruction is entered by driving Chip Select (CS#) low, shifting the instruction code
“04h” into the DI pin and then driving Chip Select (CS#) high. Note that the WEL bit is automatically reset
after Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, and Bulk
Erase instructions.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
9
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2006/12/26
EON [ EON SILICON SOLUTION INC. ]
