EN25Q40
Table 5. Manufacturer and Device Identification
OP Code
ABh
90h
9Fh
1Ch
1Ch
3013h
(M7-M0)
(ID15-ID0)
(ID7-ID0)
12h
12h
Enable Quad I/O (EQIO) (38h)
The Enable Quad I/O (EQIO) instruction will enable the flash device for Quad SPI bus operation. Upon
completion of the instruction, all instructions thereafter will be 4-bit multiplexed input/output until a
power cycle or “ Reset Quad I/O instruction “ instruction, as shown in Figure 5. The device did not
support the Read Data Bytes (READ) (03h), Dual Output Fast Read (3Bh) and Dual Input/Output
FAST_READ (BBh) modes while the Enable Quad I/O (EQIO) (38h) turns on.
Figure 5. Enable Quad I/O Sequence Diagram
Reset Quad I/O (RSTQIO) (FFh)
The Reset Quad I/O instruction resets the device to 1-bit Standard SPI operation. To execute a Reset
Quad I/O operation, the host drives CS# low, sends the Reset Quad I/O command cycle (FFh) then,
drives CS# high. The device accepts either Standard SPI ( 8 clocks ) or Quad SPI ( 2 clocks) command
cycles. For Standard SPI, DQ [3:1] are don’t care for this command, but should be driven to V
IH
or V
IL
.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
12
©2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. C, Issue Date: 2009/10/13
EON [ EON SILICON SOLUTION INC. ]
