EN25Q40
Write Enable (WREN) (06h)
The Write Enable (WREN) instruction (Figure 6) sets the Write Enable Latch (WEL) bit. The Write
Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase
(BE), Chip Erase (CE) and Write Status Register (WRSR) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (CS#) Low, sending the
instruction code, and then driving Chip Select (CS#) High.
The instruction sequence is shown in Figure 6.1 while using the Enable Quad I/O (EQIO) (38h) command.
Figure 6. Write Enable Instruction Sequence Diagram
Write Disable (WRDI) (04h)
The Write Disable instruction (Figure 7) resets the Write Enable Latch (WEL) bit in the Status Register
to a 0 or exit from OTP mode to normal mode. The Write Disable instruction is entered by driving Chip
Select (CS#) low, shifting the instruction code “04h” into the DI pin and then driving Chip Select (CS#)
high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write
Status Register, Page Program, Sector Erase, Block Erase (BE) and Chip Erase instructions.
The instruction sequence is shown in Figure 7.1 while using the Enable Quad I/O (EQIO) (38h) command.
Figure 7. Write Disable Instruction Sequence Diagram
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.eonssi.com
13
Rev. C, Issue Date: 2009/10/13
EON [ EON SILICON SOLUTION INC. ]
