EN71NS032A0
Pin Description
Symbol
A20–A16
ADQ15–ADQ0
OE#
WE#
VSSQ/VSS
VCCQ/VCC
NC
Description
Address Inputs
Multiplexed Address/Data
Output Enable input. Asynchronous relative to CLK for the
Burst mode.
Write Enable input.
Ground
Device Power Supply (1.7 V–1.95 V).
Not Contact; pin not connected internally
Ready output; indicates the status of the Burst read.
Flash Memory RDY (using default “Active HIGH”
configuration)
V
OL
= data invalid,
V
OH
= data valid.
Note: The default polarity for the pSRAM WAIT signal is
opposite the default polarity of the Flash RDY signal.
pSRAM WAIT (using default “Active HIGH” configuration)
V
OL
= data valid,
V
OH
= data invalid.
To match polarities, change bit 10 of the pSRAM Bus
Configruation Register to 0 (Active LOW WAIT). Alternately,
change bit 10 of the Flash Configuration Register to 0 (Active
LOW RDY)
Clock input. In burst mode, after the initial word is output,
subsequent active edges of CLK increment the internal
address counter. Should be at V
OL
or V
IH
while in
asynchronous mode.
Address Valid input. Indicates to device that the valid address
is present on the address inputs.
V
IL
= for asynchronous mode, indicates valid address; for
burst mode, causes starting address to be latched on rising
edge of CLK.
V
IH
= device ignores address inputs
Hardware reset input. V
IL
= device resets and returns to
reading array data
Hardware write protect input. V
IL
= disables program and
erase functions in the four outermost sectors. Should be at V
IH
for all other conditions.
Accelerated input. At Vpp , accelerates programming;
automatically places device in Accelerated Program mode. At
V
IL
, disables all program and erase functions. Should be at V
IH
for all other conditions. (Applying high voltage on MCP
package is prohibited; otherwise, internal RAM may be
damaged easily!)
Chip Enable Input for pSRAM.
Chip Enable Input for Flash. Asynchronous relative to CLK for
the Burst mode.
Control register enable (pSRAM).
Lower byte enable. DQ7~DQ0 (pSRAM)
Upper byte enable. DQ15~DQ8 (pSRAM)
Reserved for Future Use
Flash
pSRAM
●
●
●
●
●
●
●
●
●
●
●
●
●
●
RDYf/WAITp
●
●
CLK
●
●
AVD#
●
●
RESET# f
WP#f
●
●
Vppf
●
●
●
●
●
●
CE# p
CE# f
CREp
LB#p
UB#p
RFU
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
4
©2004 Eon Silicon Solution, Inc.,
www.eonssi.com
Rev. B, Issue Date: 2011/07/05
EON [ EON SILICON SOLUTION INC. ]
