EM48BM0884VTA
AC Operating Test Conditions
(VDD=3.3V±0.3V)
Item
Conditions
1.4V/1.4V
Output Reference Level
Output Load
See diagram as below
Input Signal Level
Transition Time of Input Signals
Input Reference Level
2.4V/0.4V
1ns
1.4V
AC Operating Test Characteristics
(VDD=3.3V±0.3V)
-6
-7
Symbol
Parameter
Clock Cycle Time
Units
Min. Max.
Min.
7
Max.
tCK
tAC
tCH
tCL
CL=3
CL=3
6
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
ns
ns
Access Time form CLK
CLK High Level Width
CLK Low Level Width
Data-out Hold Time
5.4
-
5.4
2.5
2.5
2.5
-
-
-
2.5
2.5
2.5
-
-
-
tOH
tHZ
tLZ
CL=3
CL=3
-
-
5.4
-
5.4
-
Data-out High Impedance
Data-out Low Impedance Time
Input Hold Time
1
1
tIH
1
-
1
-
tIS
Input Setup Time
1.5
-
-
1.5
-
-
tDQZ
tMRD
tSB
tDS
tDH
DQM Data Out Disable Latency
Mode Register Set Cycle Time
Power Down Mode Entry Time
Data-in Set-up Time
2
-
2
-
2
2
0
7
-
0
7
-
1.5
1
1.5
1
Data-in Hold Time
-
-
* All voltages referenced to VSS.
Note 5: tHZ defines the time at which the output achieve the open circuit condition and is not referenced
to output voltage levels.
Aug. 2011
9/20
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EOREX [ EOREX CORPORATION ]
