S1C33L11
● BLOCK DIAGRAM
V
DD
SS
DDE
V
V
S1C33L11
BURNIN
#RESET
#NMI
#X2SPD
A[25:18](P40–P47), A[17:1], A0/#BSL
D[15:0]
#RD
S1C33000
EA10MD[1:0]
#BUSREQ(P34)
#BUSACK(P35)
#BUSGET(P31)
DSIO
DST[2:0](P10–12)
DPCO(P13)
DCLK(P14)
TST
#WRL/#WR
#WRH/#BSH
#CE10EX
CPU Core
#CE[9:4](P55–P50)
#WAIT(P30)
#GAAS(P21)
#GARD(P31)
BCLK(P60)
Bus Control Unit
Intelligent
DMA (128 ch.)
Interrupt
Controller
#DMAREQx(K50, K51, K53, K54)
#DMAACKx(P32, P33, P04, P06)
#DMAENDx(P15, P16, P05, P07)
16-bit
Programmable
Timer (6 ch.)
EXCLx(P10–13, P15, P16)
TMx(P22–27)
High-speed
DMA (4 ch.)
8-bit
Programmable
Timer (6 ch.)
RAM
16KB
T8UFx(P10–13)
SINx(P00, P04, P27, P33)
SOUTx(P01, P05, P26, P16)
#SCLKx(P02, P06, P25, P15)
#SRDYx(P03, P07, P24, P32)
OSC3
OSC4
Serial Interface
OSC3
Standard
(4 ch.)
FSIN0(P00)
PLLS0
PLLC
OSC5SEL
FSOUT0(P01)
#FSCLK0(P02)
#FSRDY0(P03)
Prescaler/PLL/
Selector
Serial Interface
Built-in FIFO (1 ch.)
OSC5
OSC6
K50–54
K60–67
OSC5
Input Port
PuIlnl-puuptCPoonrtrol
I/O Port
USBDP
USBDM
USBVBUS
USBVDD
USB 1.1
Interface
P00–07, P10–16
P20–27, P30–35
P40–47, P50–55
P60–63
AD0–7(K60–67)
#ADTRG(K52)
AVDDE
A/D Converter
(8 ch.)
#SMWE(P34)
#SMRE(P35)
Clock
Timer
SmartMedia
Interface
SDI(P34)
SDO(P35)
SPICLK(P33)
OSC1
OSC2
FOSC1(P14/P60)
VCP
MMC (SPI mode)
Interface
OSC1/
PLL
PLLVDD
PLLVSS
Nancy
Accelerator
FPDAT[17:0]
FPFRAME
FPLINE
FPSHIFT
DRDY
CM1DAT[7:0]
CM1VREF
CM1HREF
CM1CLKOUT
CM1CLKIN
CMSTROUT
#FPCS1
#FPCS2
FPSCLK
FPA0
LCDC
(LCD I/F, Camera I/F, JPEG Codec)
MTST
SCANEN
FPSO
FPVIN1
FPVIN2
LCDVDD
CNF2
GPIO[3:0]
Fig. 1 S1C33L11 Functional Block Diagram
3
EPSON [ EPSON COMPANY ]
