S1C33L11
● PIN LAYOUT
U
T
N.C.
FPDAT16 FPDAT17 GPIO0
GPIO3
P05
P21
OSC3
OSC4
PLLC
V
DDE
SS
OSC2
P61
OSC1
PLLVSS
MTST
TST
VCP
PLLVDD
N.C.
PFBGA-208pin
(SOUT1/
(#DWE/
#DMAEND2) #GAAS)
FPDAT11 FPDAT12 FPDAT15 CNF2
VDD
P03
P01
P00
VSS
EA10MD1
V
VDD
BURNIN
VSS
USBDP
USBDM
USBVBUS
(#SRDY0/
#FSRDY0)
(SOUT0/
FSOUT0)
(SIN0/
FSIN0)
Top View
R
P
N
M
L
FPDAT9
FPDAT8
FPDAT6
FPDAT3
FPDAT0
DRDY
FPDAT13 FPDAT14 GPIO1
P07
P04
P20
#RESET
PLLS0
P23
SCANEN P26
P27
K50
USBVDD
K52
(#SRDY1/
(SIN1/
(#DRD)
(TM1)
(TM4/SOUT2) (TM5/SIN2)
(#DMAREQ0)
#DMAEND3) #DMAACK2)
U
T
VSS
FPDAT10 LCDVDD
GPIO2
P06
P02
P22
EA10MD0 #NMI
P24
(TM2/#SRDY2) (TM3/
#SCLK2)
P25
P62
K51
K53
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
(#SCLK1/
(#SCLK0/
(TM0)
(#DMAREQ1) (#DMAREQ2) (#ADTRG)
#DMAACK3) #FSCLK0)
FPDAT4
FPDAT5
FPDAT1
#FPCS2
LCDVDD
FPDAT7
FPDAT2
FPFRAME
FPSCLK
FPA0
K54
VDD
#CE10EX
VDDE
(#DMAREQ3)
(#CE9&10EX)
VSS
#CE8
#CE7
OSC5SEL #CE9
(#RAS1/
#CE14/
(#RAS0/
#CE13/
(#CE17/
#CE17&18/
#RAS3/P54) #RAS2/P53)
P55)
#FPCS1
FPSHIFT
FPLINE
#X2SPD
VSS
P63
OSC5
Index
K
J
#CE4
#CE6
#CE5
OSC6
(#CE11/
#CE11&12/
P50)
(#CE7&8/P52) (#CE15/
#CE15&16/
17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1
P51)
FPSO
VSS
#WRH
(#BSH)
#RD
D3
#WRL
(#WR/#WE)
VDD
A1 Corner
Bottom View
H
G
F
CM1CLKOUT
VDD
CMSTROUT
FPVIN1
V
SS
D0
VDDE
BCLK
(P60/FOSC1)
U
T
CM1HREF FPVIN2
CM1CLKIN
V
V
V
DD
D4
D1
D2
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
LCDVDD
CM1VREF CM1DAT7 CM1DAT6
SS
D7
D5
D6
E
D
C
B
A
CM1DAT4 CM1DAT5
CM1DAT2 CM1DAT3
V
SS
DD
V
SS
DDE
D13
A1
D9
D8
V
P15
DSIO
VDD
AVDDE
K64
VSS
P30
A23
A20
A17
A12
A11
A8
A10
A9
D10
D15
D11
D12
D14
N.C.
17
(EXCL4/
#DMAEND0/
#SCLK3)
(#WAIT/
#CE4&5)
(P42)
(P45)
CM1DAT1 CM1DAT0 DST1
(P11/EXCL1/
VDDE
DPCO
P32
K61
#HCAS
A21
A18
A16
A14
A13
A7
(P13/EXCL3/ (#DMAACK0/ (AD4)
(AD1)
(P40/A25)
(P44)
(P47)
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
T8UF1)
T8UF3)
#SRDY3)
A1 Corner
P16
DST0
DCLK
P34
P33
K65
K63
K60
#LCAS
VDD
VDDE
VSS
A4
A0
(EXCL5/
(P10/EXCL0/ (P14/FOSC1) (#BUSREQ/
(#DMAACK1/ (AD5)
(AD3)
(AD0)
(P41/A24)
(#BSL)
#DMAEND1/ T8UF0)
SOUT3)
#CE6/#SMWE/ SIN3/SPICLK)
SDI)
N.C.
DST2
VSS
P35
P31
K67
K66
K62
A22
A19
A15
A6
A5
A3
A2
(P12/EXCL2/
T8UF2)
(#BUSACK/
(#BUSGET/
(AD7)
(AD6)
(AD2)
(P43)
(P46)
#SMRE/SDO) #GARD)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Bold: The terminal (signal) name of a default setup.
Fig. 2 Pin Layout Diagram (PFBGA-208pin)
NOTICE:
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko
Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of
any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that
this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual
property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this
material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the
subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export
license from the Ministry of International Trade and Industry or other approval from another government agency.
© Seiko Epson Corporation 2003, All right reserved.
● EPSON Electronic Devices Website
SEIKO EPSON CORPORATION
http://www.epsondevice.com
ELECTRONIC DEVICES MARKETING DIVISION
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Document code: 404625402
First issue July, 2003
L
Printed November, 2003 in Japan
EPSON [ EPSON COMPANY ]
