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S1L54424 参数 Datasheet PDF下载

S1L54424图片预览
型号: S1L54424
PDF下载: 下载PDF文件 查看货源
内容描述: 高密度门阵列 [HIGH DENSITY GATE ARRAY]
分类和应用:
文件页数/大小: 12 页 / 96 K
品牌: EPSON [ EPSON COMPANY ]
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DATA SHEET  
ASIC  
S1L50000  
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EEA CUSTOMER ENGINEERING  
To help customers implement their design of EEA ASIC’s, we offer training at our design centers  
and at customer sites when required.  
When a design is started, an EEA engineer is assigned to the project and will remain with the  
project through its completion. EEA engineers will work with the customer on design, software and  
other technical issues. When the design files are transferred to EEA, the assigned engineer will  
verify the design’s integrity and prepare it for place and route. The EEA Customer Engineering  
Group provides all technical customer-support services including:  
Pre-Sale Technical Support  
Customer Training  
Design Assistance  
Custom Cell Development  
Place and Route  
Scan Insertion and ATPG  
Netlist Conversion and Synthesis  
Software Documentation  
Simulation Support  
Turnkey Design  
Design Verification  
Static Timing Analysis  
JTAG Insertion  
Test Vector Conversion  
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EDA/CAE SUPPORT  
Schematic Capture  
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Viewlogic (Synopsys): Viewdraw  
EEA: Auklet (ECS)  
Synthesis  
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Synopsys: DesignCompiler  
Exemplar Logic: Leonardo  
Simulation  
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Cadence: Verilog-XL  
Synopsys: VSS (VHDL)  
Avant!: Polaris (Purespeed)  
Viewlogic (Synopsys): Viewsim  
Modeltech: V-System (VHDL)  
DFT  
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Synopsys: TestCompiler+  
Viewlogic (Synopsys): TestGen (Sunrise)  
Place & Route  
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Cadence: GateEnsemble  
Avant!: Aquarius-GA (Apollo)  
Delay Calculation (Post-Route)  
EEA: Peacock (EXDT)  
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10  
EPSON ELECTRONICS AMERICA, INC.  
150 River Oaks Pkwy  
San Jose, CA 95134  
Tel: (408) 922-0200  
Fax: (408) 922-0238