SPECIFICATIONS
6.2. S1D13305
V
DD = 4.5 to 5.5V, VSS = 0V, T
a
= –20 to 75°C
Rating
Typ.
5.0
Parameter
Symbol
Condition
Unit
Min.
4.5
2.0
—
Max.
5.5
6.0
2.0
5.0
15
Supply voltage
V
DD
OH
V
V
Register data retention voltage
Input leakage current
V
—
I
LI
LO
opr
V
V
I
I
= VDD. See note 5.
= VSS. See note 5.
0.05
0.10
11
µA
µA
mA
Output leakage current
Operating supply current
I
—
I
See note 4.
—
Sleep mode,
VOSC1 = VCS = VRD = VDD
Quiescent supply current
IQ
—
0.05
20.0
µA
Oscillator frequency
External clock frequency
Oscillator feedback resistance
TTL
f
OSC
CL
1.0
1.0
0.5
—
—
10.0
10.0
3.0
MHz
MHz
MΩ
Measured at crystal,
47.5% duty cycle.
See note 6.
f
Rf
1.0
HIGH-level input voltage
LOW-level input voltage
V
IHT
See note 1.
See note 1.
0.5VDD
—
—
V
DD
V
V
V
ILT
VSS
0.2VDD
I
OH = –5.0 mA.
See note 1.
OL = 5.0 mA. See note 1.
HIGH-level output voltage
V
OHT
2.4
—
—
—
—
V
V
LOW-level output voltage
CMOS
V
OLT
I
VSS + 0.4
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
Open-drain
V
IHC
ILC
OHC
See note 2.
See note 2.
0.8VDD
—
—
—
—
V
DD
V
V
V
V
V
VSS
0.2VDD
—
V
I
I
OH = –2.0 mA. See note 2.
OH = 1.6 mA. See note 2.
VDD – 0.4
V
V
OLC
OLN
—
V
SS + 0.4
LOW-level output voltage
Schmitt-trigger
IOL = 6.0 mA.
—
—
V
SS + 0.4
V
Rising-edge threshold voltage
Falling-edge threshold voltage
Notes:
V
T+
T–
See note 3.
See note 3.
0.5VDD 0.7VDD 0.8VDD
0.2VDD 0.3VDD 0.5VDD
V
V
V
1. D0 to D7, A0, CS, RD, WR, VD0 to VD7, VA0 to VA15, VRD, VWR and VCE are TTL-level inputs.
2. SEL1 is CMOS-level inputs. YD, XD0 to XD3, XSCL, LP, WF, YDIS are CMOS-level outputs.
3. RES is a Schmitt-trigger input. The pulsewidth on RES must be at least 200 µs. Note that pulses of more than a few seconds
will cause DC voltages to be applied to the LCD panel.
4.
fOSC = 10 MHz, no load (no display memory), internal character generator, 256 × 200 pixel display. The operating
supply current can be reduced by approximately 1 mA by setting both CLO and the display OFF.
5. VD0 to VD7 and D0 to D7 have internal feedback circuits so that if the inputs become high-impedance, the input
state immediately prior to that is held. Because of the feedback circuit, input current flow occurs when the
inputs are in an intermediate state.
6. Because the oscillator circuit input bias current is in the order of µA, design the printed circuit board so as to
reduce leakage currents.
8
EPSON
S1D13305 Series
Technical Manual
EPSON [ EPSON COMPANY ]
