SED1530 Series
s
BLOCK DIAGRAM (SED1530D
0B
)
V
SS
O0
O99 O100
O15 COMS
···············································
·····················
V3
V5
V2
V4
Segment driver
Common driver
Shift register
CAP1+
CAP1–
CAP2+
CAP2–
CAP3–
Initial display line register
Line address decoder
I/O buffer circuit
Power supply
circuit
Display data latch
V
R
Output
status
selector
circuit
132 x 65-dot
display data RAM
Column address decoder
Page address
register
8-bit column address counter
Display timing
generator circuit
8-bit column address register
FRS
FR
CL
DYO
DOF
M//S
Bus holder
Command decoder
Status
register
Line counter
V
OUT
COM S
V1
V
DD
Oscillator
VS1
Microprocessor interface
I/O buffer
CS1 CS2
A0
RD WR C86 P/S RES
(E) (R/W)
D7 D6
D5
(SI) (SCL)
D4
D3
D2
D1
D0
3
EPSON [ EPSON COMPANY ]
