EFST
Read Mode
To read array data from the outputs, the system must
drive the
CE
and
OE
pins to V
IL
.
CE
is the power
control and selects the device.
OE
is the output control
and gates array data to the output pins.
WE
should
remain at V
IH
. The internal state machine is set for
reading array data upon device power-up, or after a
hardware reset. This ensures that no spurious alteration
of the memory content occurs during the power
transition.
No command is necessary in this mode to obtain array
data. Standard microprocessor’s read cycles that assert
valid addresses on the device address inputs produce
valid data on the device data outputs. The device
remains enabled for read access until the command
register contents are altered.
See “Read Command” section for more information.
Refer to the AC Read Operations Table 9 for timing
specifications and to Figure 5 for the timing diagram. I
CC1
in the DC Characteristics Table 8 represents the active
current specification for reading array data.
F49L040A
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically enables
this mode when addresses remain unchanged for over
250ns. The automatic sleep mode is independent of the
CE
,
WE
, and
OE
control signals. Standard address
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
and always available to the system. I
CC4
in the DC
Characteristics Table 8 represents the automatic sleep
mode current specification.
Output Disable Mode
With the
OE
is at a logic high level (V
IH
), outputs from
the devices are disabled. This will cause the output pins
in a high impedance state
Standby Mode
When
CE
held at V
CC
± 0.3V, the device enter
CMOS Standby mode. If
CE
held at V
IH
, but not within
the range of V
CC
± 0.3V, the device will still be in the
standby mode, but the standby current will be larger.
If the device is deselected during auto algorithm of
erasure or programming, the device draws active
current I
CC2
until the operation is completed. I
CC3
in
the DC Characteristics Table 8 represents the standby
current specification.
The device requires standard access time (t
CE
) for
read access from either of these standby modes,
before it is ready to read data.
Write Mode
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive
WE
and
CE
to V
IL
, and
OE
to V
IH
. The “Program Command” section
has details on programming data to the device using
standard command sequences.
An erase operation can erase one sector, multiple sectors,
or the entire device. Table 1 indicate the address space
that each sector occupies. A “sector address” consists of
the address bits required to uniquely select a sector. The
“Software Command Definitions” section has details on
erasing a sector or the entire chip, or suspending/resuming
the erase operation.
When the system writes the auto-select command
sequence, the device enters the auto-select mode. The
system can then read auto-select codes from the internal
register (which is separate from the memory array) on
DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the Auto-select Mode and Auto-select
Command sections for more information. I
CC2
in the DC
Characteristics Table 8 represents the active current
specification for the write mode. The “AC Characteristics”
section contains timing specification Table 10 and timing
diagrams for write operations.
Sector Protect / Un-protect Mode
The hardware sector protect feature disables both
program and erase operations in any sector. The
hardware sector unprotect feature re-enables both the
program and erase operations in previously protected
sectors. Sector protect/unprotect can be implemented
A6 pin via programming equipment.
Elite Flash Storage Technology Inc.
Publication Date : Apr. 2005
Revision: 1.0
6/41
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
