EFST
4. PIN CONFIGURATIONS
4.1
48-pin TSOP
F49L400UA/F49L400BA
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RY/BY
NC
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
G ND
DQ15/A-1
DQ 7
DQ14
DQ 6
DQ13
DQ 5
DQ12
DQ 4
VCC
DQ11
DQ 3
DQ10
DQ 2
DQ 9
DQ 1
DQ 8
DQ 0
OE
G ND
CE
A0
F49L400U/BA
4.2
Pin Description
Symbol
Pin Name
Address Input
Data Input/Output
Q15 (Word mode) /
LSB addr (Byte Mode)
Chip Enable
Output Enable
Write Enable
Reset
Word/Byte selection input
Ready/Busy
Power Supply
Ground
No connection
Functions
To provide memory addresses.
To output data when Read and receive data when Write.
The outputs are in tri-state when OE or CE is high.
To bi-direction date I/O when
BYTE
is High
To input address when
BYTE
is Low
To activate the device when CE is low.
To gate the data output buffers.
To control the Write operations.
Hardware Reset Pin/Sector Protect Unprotect
To select word mode or byte mode
To check device operation status
To provide power
A0~A17
DQ0~DQ14
DQ15/A-1
CE
OE
WE
RESET
BYTE
RY/
BY
V
CC
GND
NC
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006
Revision: 1.1
2/47
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
