EFST
7. FUNCTIONAL DESCRIPTION
7.1 Device operation
This section describes the requirements and use
of the device bus operations, which are initiated
through the internal command register. The
register is composed of latches that store the
command, address and data information needed
to execute the command. The contents of the
F49L400UA/F49L400BA
register serve as inputs to the internal state
machine. The state machine outputs dictate the
function
of
the
device.
The
F49L400UA/F49L400BA features various bus
operations as Table 3.
Table 3. F49L400UA/F49L400BA Operation Modes Selection
ADDRESS
DESCRIPTION
CE
OE
WE
RESET
A17 A11
|
|
A12 A10
A9
A8
|
A7
X
AIN
AIN
X
X
A6
A5
|
A2
A1 A0
DQ0~DQ7
Reset(3)
Read
Write
Output Disable
Standby
Sector Protect(2)
Sector Unprotect(2)
Temporary sector unprotect
Auto-select
Notes:
X
L
L
L
V
CC
±
0.3V
L
L
X
X
L
H
H
X
H
H
X
X
H
L
H
X
L
L
X
L, Vss±
0.3V(3)
H
H
H
V
CC
±
0.3V
V
ID
V
ID
V
ID
See Table 4
SA
SA
X
X
X
X
High Z
Dout
DIN
High Z
High Z
L
H
X
X
H
H
L
L
DIN
DIN
DIN
X
X
AIN
1.
L= Logic Low = V
IL
, H= Logic High = V
IH
, X= Don't Care, SA= Sector Address, V
ID
=11.5V to 12.5V.
AIN= Address In, DIN = Data In, Dout = Data Out.
2. The sector protect and unprotect functions may also be implemented via programming equipment.
3. See “Reset Mode” section.
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006
Revision: 1.1
5/47
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
