ESMT
M12L32162A
Page Read & Write Cycle at Same Bank @ Burst Length=4
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CLOCK
CKE
HIGH
CS
tRCD
RAS
*Note2
CAS
ADDR
BA
Ra
Cb0
Ca0
Cc0
Cd0
A10/AP
Ra
tRDL
CL=2
Qa0
Qb0
Qb1
Qb0
Dc0
Dc0
Dc1
Dd1
Qb2
Qb1
Qa1
Qa0
Dd0
DQ
Qa1
Dc1 Dd0
Dd2
CL=3
tCDL
WE
*Note3
*Note1
DQM
Read
(A-Bank)
Write
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
: Don't care
*Note :1.To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus
contention.
2.Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
3.DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2009
Revision : 1.2 14/29
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
