ESMT
FUNCTIONAL BLOCK DIAGRAM
M12S16161A
Operation Temperature Condition -40°C~85°C
I/O Control
LWE
LDQM
Bank Select
Data Input Register
Row Buffer
Refresh Counter
Row Decoder
Sense AMP
Output Buffer
512K x 16
512K x 16
Address Register
LRAS
CLK
DQi
CLK
ADD
LCBR
LRAS
Col. Buffer
Column Decoder
Latency & Burst Length
LCKE
Programming Register
LCBR
LWE
LCAS
LWCBR
LDQM
Timing Register
CKE
CS
RAS
CAS
WE
L(U)DQM
PIN FUNCTION DESCRIPTION
Pin
CLK
CS
CKE
A0 ~ A10/AP
BA
RAS
Name
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with
CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS ,
WE
active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
CAS
Column Address Strobe
WE
Write Enable
Data Input / Output Mask
L(U)DQM
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Sep. 2007
Revision
:
1.0
2/30
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
