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M12S16161A-6BIG 参数 Datasheet PDF下载

M12S16161A-6BIG图片预览
型号: M12S16161A-6BIG
PDF下载: 下载PDF文件 查看货源
内容描述: 512K X 16位X 2Banks同步DRAM [512K x 16Bit x 2Banks Synchronous DRAM]
分类和应用: 存储内存集成电路动态存储器
文件页数/大小: 30 页 / 622 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
Parameter
CLK cycle time
CLK to valid
output delay
CAS Latency =3
CAS Latency =2
CAS Latency =3
CAS Latency =2
Symbol
t
CC
t
SAC
t
OH
t
CH
t
CL
t
SS
t
SH
t
SLZ
t
SHZ
-6
Min
6
8
-
-
2
2
2
2
1
1
-
-
5.5
6
Max
1000
5.5
6
Min
7
8.6
-
-
2
2.5
2.5
2
1
1
-
-
6
6
6
6
-7
Max
1000
M12S16161A
Operation Temperature Condition -40°C~85°C
Note
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
1
1
2
3
3
3
3
2
Output data hold time
CLK high pulse width
CLK low pulse width
Input setup time
Input hold time
CLK to output in Low-Z
CLK to output in
Hi-Z
CAS Latency =3
CAS latency =2
*All AC parameters are measured from half to half.
Note:
1.Parameters depend on programmed CAS latency.
2.If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter.
3.Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to the
parameter.
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Sep. 2007
Revision
:
1.0
6/30