ESMT
BLOCK DIAGRAM
CLK
CKE
Address
Mode
Register
Clock
Generator
M12S64322A
Bank D
Bank C
Bank B
Row
Address
Buffer
&
Refresh
Counter
Row Decoder
Bank A
Sense Amplifier
Command Decoder
Control Logic
CS
RAS
CAS
WE
Data Control Circuit
Input & Output
Buffer
Latch Circuit
Column
Address
Buffer
&
Refresh
Counter
DQM0~3
Column Decoder
DQ
PIN DESCRIPTION
PIN
CLK
CS
CKE
A0 ~ A10
BA0 , BA1
RAS
NAME
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
INPUT FUNCTION
Active on the positive going edge to sample all inputs
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and DQM0-3.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
Row / column address are multiplexed on the same pins.
Row address : RA0~RA10, column address : CA0~CA7
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Latches row addresses on the positive going edge of the CLK with
RAS low.
Enables row access & precharge.
Latches column address on the positive going edge of the CLK with
CAS
Column Address Strobe
CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS ,
WE
active.
WE
Write Enable
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2007
Revision: 1.0
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ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
