ESMT
Thermal Resistance[6]
Parameter
θ
JA
θ
JC
M24L48512DA
Description
Test Conditions
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
VFBGA
55
17
Unit
°C/W
°C/W
Thermal Resistance (Junction to Ambient)
Thermal Resistance (Junction to Case)
AC Test Loads and Waveforms
Parameters
R1
R2
R
TH
V
TH
3.0V V
CC
22000
22000
11000
1.50
Unit
Ω
Ω
Ω
V
Switching Characteristics (Over the Operating Range)[7]
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
Description
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE1 LOW and CE2 HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[8, 9]
OE HIGH to High Z[8, 9]
CE1 LOW and CE2 HIGH to Low Z[8,
9]
2
25
0
55
45
45
0
60
45
45
0
5
25
2
25
5
70
60
55
0
–55
Min.
55
[11]
55
5
55
25
5
25
5
25
10
8
60
25
5
25
Max.
Min.
60
60
10
70
35
–60
Max.
Min.
70
70
–70
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE1 HIGH and CE2 LOW to High Z[8,
9]
[11]
t
SK
Address Skew
Write Cycle[10]
t
WC
Write Cycle Time
t
SCE
CE1 LOW and CE2 HIGH to Write End
t
AW
t
HA
Address Set-up to Write End
Address Hold from Write End
Notes:
7. Test conditions assume signal transition time of 1 V/ns or higher, timing reference levels of V
CC(typ)
/2, input pulse levels of 0V to
V
CC(typ)
, and output loading of the specified I
OL
/I
OH
and 30-pF load capacitance.
8. t
HZOE
, t
HZCE
, and t
HZWE
transitions are measured when the outputs enter a high-impedance state.
9. High-Z and Low-Z parameters are characterized and are not 100% tested.
10.The internal write time of the memory is defined by the overlap of
WE
, CE1 = V
IL
, and CE2 = V
IH
. All signals must be ACTIVE
to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing
should be referenced to the edge of the signal that terminates write.
11.To achieve 55-ns performance, the read access should be CE controlled. In this case t
ACE
is the critical parameter and t
SK
is
satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable
within 10 ns after the start of the read cycle.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.1
4/12
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
