ESMT
SIMPLIFIED TRUTH TABLE
COMMAND
Mode Register Set
Extended Mode Register
Set
Auto Refresh
Entry
Self Refresh
Exit
CKEn-1 CKEn CS
H
H
H
L
H
H
X
X
H
L
H
X
X
L
L
L
L
H
L
L
RAS
L
L
L
H
X
L
H
CAS
L
L
L
H
X
H
L
WE
M52D32162A
DQM BA A10/AP
X
X
X
X
X
X
V
V
Register
L
L
H
H
X
H
H
A11, Note
A9~A0
OP CODE
1,2
OP CODE
1,2
X
X
Row Address
Column
L
H
3
3
3
3
4
Refresh
Bank Active & Row Addr.
Auto Precharge Disable
Read &
Column Address
Write & Column
Address
Burst Stop
Precharge
Clock Suspend or
Active Power Down
Precharge Power Down Mode
Bank Selection
Both Banks
Entry
Exit
Entry
Exit
DQM
No Operation Command
Deep Power Down Mode
Entry
Exit
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
H
H
H
H
L
H
L
H
H
H
H
L
X
X
X
L
H
L
H
L
L
L
H
L
X
H
L
H
L
H
L
L
X
H
H
L
X
V
X
X
H
X
V
X
X
H
H
X
L
H
H
X
V
X
X
H
X
V
X
H
H
X
L
L
L
X
V
X
X
H
X
V
X
H
L
X
X
X
X
X
X
X
V
L
H
X
L
H
X
Address
(A0~A7)
4,5
Column
4
Address
4,5
(A0~A7)
V
X
X
6
4
4
X
X
V
X
X
X
X
X
X
7
X
L
H
(V= Valid, X= Don’t Care, H= Logic High , L = Logic Low)
Note:
1. OP Code: Operation Code
A0~ A11/AP, BA: Program keys.(@MRS). BA=0 for MRS and BA=1 for EMRS.
2.
3.
MRS/EMRS can be issued only at both banks precharge state.
A new command can be issued after 2 clock cycle of MRS.
Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by “Auto”.
Auto / self refresh can be issued only at both banks precharge state.
4.
BA: Bank select address.
If “Low”: at read, write, row active and precharge, bank A is selected.
If “High”: at read, write, row active and precharge, bank B is selected.
If A10/AP is “High” at row precharge, BA ignored and both banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read /write command can be issued after the end of burst.
New row active of the associated bank can be issued at t
RP
after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but
makes
Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Elite Semiconductor Memory Technology Inc.
Publication Date
:
May. 2007
Revision
:
1.4
11/30
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
