ESMT
Read & Write Cycle at Same Bank @Burst Length = 4
0
CLOCK
M52D32162A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HIGH
CKE
*Note1
t
RC
CS
t
RCD
RAS
*Note2
CAS
ADDR
Ra
Ca0
Rb
Cb0
BA
A10/AP
Ra
Rb
t
OH
CL=2
QC
CL=3
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
t
R AC
*Note3
t
S AC
Qa0
t
S H Z
t
O H
Qa1
Qa2
Qa3
*Note4
t
RDL
Db0
Db1
Db2
Db3
t
R AC
*Note3
t
S AC
t
S H Z
*Note4
t
RDL
WE
DQ M
Row Active
(A- Bank)
Read
(A- Ban k)
Precharge
(A- Bank)
Row Active
(A- Bank)
W r ite
(A- Ban k)
Precharge
(A- Bank)
: Don't care
*Note:
1.Minimum row cycle times is required to complete internal DRAM operation.
2.Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row
precharge. Last valid output will be Hi-Z(t
SHZ
) after the clock.
3.Access time from Row active command. tcc*(t
RCD
+CAS latency-1)+t
SAC
4.Ouput will be Hi-Z after the end of burst.(1,2,4,8 bit burst)
Burst can’t end in Full Page Mode.
Elite Semiconductor Memory Technology Inc.
Publication Date
:
May. 2007
Revision
:
1.4
15/30
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
