ES6128 PRODUCT BRIEF
ES6128 PIN DESCRIPTION
ES6128 PIN DESCRIPTION
Table 1
Name
VEE
ES6128 Pin Description
Pin Numbers
1,18, 27, 59, 68, 75,
92, 99, 104, 130,
148, 157, 159, 164,
183, 193, 201
2-7, 10-16, 19-23,
204-207
8, 17, 26, 34, 43,
60, 67, 76, 84, 91,
98, 103, 120, 129,
138, 147, 156, 163,
171, 177, 184, 192,
200, 208
9, 35, 44, 83, 121,
139, 172
24
I/O
Definition
P
I/O power supply.
LA[21:0]
VSS
O
RISC port address bus.
G
Ground.
VCC
RESET#
TDMDX
RSEL
P
I
O
I
Core power supply.
Reset input; (5V tolerant input).
TDM transmit data output.
LCS3 ROM Boot Data Width Select. Strapped to VCC or ground via 4.7-kΩ
resistor; read only during reset.
RSEL
0
1
Selection
16-bit ROM
8-bit ROM
25
TDMDR
TDMCLK
TDMFS
TDMTSC#
TWS
SEL_PLL2
28
29
30
31
I
I
I
O
O
I
TDM receive data input; (5V tolerant input).
TDM clock input; (5V tolerant input).
TDM frame sync input; (5V tolerant input).
TDM output enable.
Audio transmit frame sync output.
System and DSCK output clock frequency selection is made at the rising edge of
RESET#. The matrix below lists the available clock frequencies and their
respective PLL bit settings. Strapped to VCC or ground via 4.7-kΩ resistor; read
only during reset.
SEL_PLL2
0
SEL_PLL1
0
0
1
1
0
0
1
1
SEL_PLL0
0
1
0
1
0
1
0
1
PLL Settings
DCLK
× 4.5
DCLK
×
5.0
Bypass
DCLK
×
4.0
DCLK
×
4.25
DCLK
×
4.75
DCLK
×
5.5
DCLK
×
6.0
32
0
0
0
1
1
1
1
TSD0
33
SEL_PLL0
ESS Technology, Inc.
O
I
Audio transmit serial data output 0.
Refer to the description and matrix for SEL_PLL2 pin 32.
SAM0481B-052705
3
ESS [ ESS Technology,Inc ]
