EtronTech
T0
CLK
T1
T2
DQM
1M x 16 SDRAM
T3
T4
T5
EM636165-XXI
T6
T7
T8
1 Clk Interval
COM MAND
NOP
NOP
BANKA
ACTIVATE
NOP
READ A
WRITE A
NOP
NOP
NOP
CAS# latency=1
tCK1, DQ's
CAS# latency=2
tCK2, DQ's
DIN A0
Must be Hi-Z before
the Write Command
DIN A0
DIN A1
DIN A2
DIN A3
DIN A1
DIN A2
DIN A3
: "H" or "L"
Read to Write Interval
(Burst Length
≥
4, CAS# Latency = 1, 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
COM MAND
NOP
NOP
READ A
NOP
NOP
WRITE B
NOP
NOP
NOP
CAS# latency=1
tCK1, DQ's
CAS# latency=2
tCK2, DQ's
DOUT A0
DIN B0
DIN B 1
DIN B2
DIN B3
Must be Hi-Z before
the Write Command
DIN B0
DIN B 1
DIN B2
DIN B3
: "H" or "L"
Read to Write Interval
(Burst Length
≥
4, CAS# Latency = 1, 2)
A read burst without the auto precharge function may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank. The following figure shows the optimum time that
BankPrecharge/ PrechargeAll command is issued in different CAS# latency.
T0
CLK
Bank,
Col A
Bank,
Row
T1
T2
T3
T4
T5
T6
T7
T8
ADDRESS
Bank(s)
t
RP
COMM AND
READ A
NOP
NOP
NOP
Precharge
NOP
NOP
Activate
NOP
CAS# latency=1
tCK1, DQ's
CAS# latency=2
tCK2 , DQ's
CAS# latency=3
tCK3 , DQ's
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
Read to Precharge
(CAS# Latency = 1, 2, 3)
Preliminary
8
Rev. 1.1
Apr. 2005
ETRON [ ETRON TECHNOLOGY, INC. ]
