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EM636327Q-6 参数 Datasheet PDF下载

EM636327Q-6图片预览
型号: EM636327Q-6
PDF下载: 下载PDF文件 查看货源
内容描述: 512K ×32高速同步图形DRAM ( SGRAM ) [512K x 32 High Speed Synchronous Graphics DRAM(SGRAM)]
分类和应用: 动态存储器
文件页数/大小: 78 页 / 1387 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
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EtronTech
Operation Mode
EM636327
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 2 shows the truth table for the operation commands.
Table 2. Truth Table (Note (1), (2) )
Command
BankActivate & Masked Write Disable
BankActivate & Masked Write Enable
BankPrecharge
PrechargeAll
Write
Block Write Command
Write and AutoPrecharge
Block Write and AutoPrecharge
Read
Read and Autoprecharge
Mode Register Set
Special Mode Register Set
No-Operation
Burst Stop
Device Deselect
AutoRefresh
SelfRefresh Entry
SelfRefresh Exit
State
Idle
(3)
Idle
(3)
Any
Any
Active
(3)
Active
(3)
Active
(3)
Active
(3)
Active
(3)
Active
(3)
Idle
Idle
(5)
Any
Active
(4)
Any
Idle
Idle
Idle
(SelfRefresh)
CKE
n-1
CKE
n
DQM
(7)
BS A
9
A
0-8
CS# RAS# CAS# WE# DSF
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
L
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
H
L
L
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
V
V
V
X
V
V
V
V
V
V
V
X
X
X
X
X
X
X
X
X
X
X
X
V
V
L
H
L
L
H
H
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
V
V
X
X
V
V
V
V
V
V
V
V
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
X
H
L
X
H
L
X
L
L
L
L
H
H
H
H
H
H
L
L
H
H
X
L
L
X
H
X
X
H
X
X
H
X
H
H
H
H
L
L
L
L
L
L
L
L
H
H
X
L
L
X
H
X
X
H
X
X
H
X
H
H
L
L
L
L
L
L
H
H
L
L
H
L
X
H
H
X
H
X
X
H
X
X
H
X
L
H
L
L
L
H
L
H
L
L
L
H
X
L
X
L
L
X
X
X
X
L
X
X
L
X
X
Clock Suspend Mode Entry
Power Down Mode Entry
Active
Any
(6)
Active
Any
(PowerDown)
Clock Suspend Mode Exit
Power Down Mode Exit
Data Write/Output Enable
Data Mask/Output Disable
Active
Active
H
X
H
X X X
X
X
X
X
Note:
1. V=Valid X=Don't Care L=Low level H=High level
2. CKE
n
signal is input level when commands are provided.
CKE
n-1
signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. The Special Mode Register Set is also available in Row Active State.
6. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
7. DQM0-3
Preliminary
5
December
1998