欢迎访问ic37.com |
会员登录 免费注册
发布采购

EM6A9320_06 参数 Datasheet PDF下载

EM6A9320_06图片预览
型号: EM6A9320_06
PDF下载: 下载PDF文件 查看货源
内容描述: 4M ×32 DDR SDRAM [4M x 32 DDR SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 17 页 / 363 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
 浏览型号EM6A9320_06的Datasheet PDF文件第3页浏览型号EM6A9320_06的Datasheet PDF文件第4页浏览型号EM6A9320_06的Datasheet PDF文件第5页浏览型号EM6A9320_06的Datasheet PDF文件第6页浏览型号EM6A9320_06的Datasheet PDF文件第8页浏览型号EM6A9320_06的Datasheet PDF文件第9页浏览型号EM6A9320_06的Datasheet PDF文件第10页浏览型号EM6A9320_06的Datasheet PDF文件第11页  
EtronTech
4Mx32 DDR SDRAM
EM6A9320
Extended Mode Register Set (EMRS)
The Extended Mode Register Set stores the data for enabling or disabling DLL and selecting output driver
strength. The default value of the extended mode register is not defined, therefore must be written after power
up for proper operation. The extended mode register is written by asserting low on CS#, RAS#, CAS#, and
WE#. The state of A0, A2 ~ A5, A7 ~ A11and BA1 is written in the mode register in the same cycle as CS#,
RAS#, CAS#, and WE# going low. The DDR SDRAM should be in all bank precharge with CKE already high
prior to writing into the extended mode register. A1 and A6 are used for setting driver strength to normal, weak
or matched impedance. Two clock cycles are required to complete the write operation in the extended mode
register. The mode register contents can be changed using the same command and clock cycle requirements
during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0
is used for EMRS. Refer to the table for specific codes.
Extended Mode Resistor Bitmap
BA1
0
BA0
1
A11
A10
A9
A8
RFU must be set to “0”
A7
A6
DS1
A5
A4
A3
A2
RFU must be set to “0”
A1
DS0
A0
DLL
BA0 Mode
0
MRS
1 EMRS
A6
0
0
1
1
A1
Drive Strength
Strength
Comment
0
Full
100%
1
SSTL-2 weak
60%
0
RFU
RFU Do not use
1 Matched impedance 30%
Output driver matches impedance
A0
DLL
0
Enable
1 Disable
Power up Sequence
Power up must be performed in the following sequence.
1) Apply power to V
DD
before or at the same time as V
DDQ,
V
TT
and V
REF
when all input signals are held
"NOP" state and maintain CKE “LOW”.
2) Start clock and maintain stable condition for minimum 200us.
3) Issue a “NOP” command and keep CKE “HIGH”
4) Issue a “Precharge All” command.
5) Issue EMRS – enable DLL.
6) Issue MRS – reset DLL. (An additional 200 clock cycles are required to lock the DLL).
7) Precharge all banks of the device.
8) Issue two or more Auto Refresh commands.
9) Issue MRS – with A8 to low to initialize the mode register.
7
Rev 0.6
May. 2006