MP1230A/31A/32A
TIMING DIAGRAM
V
IH
V
IL
t
WR
50%
t
DS
50%
50%
t
CS
50%
t
CH
50%
CS, BYTE1/BYTE2
V
IH
WR
V
IL
V
IH
DATA BITS
V
IL
t
DH
50%
t
S
SETTLED TO
+0.01%
I
OUT1
, I
OUT2
DEFINITION OF CONTROL SIGNALS:
CS:
WR1:
Chip Select.(Active low)
It will enable WR1.
Write 1 (Active low)
The WR1 is used to load the digital data bits (DB) into
the input latch.
I
OUT2
:
R
FB
:
DAC Current Output 2 Bus.
I
OUT2
is a complement of I
OUT1
.
Feedback Resistor.
This internal feedback resistor should always be used
(not an external resistor) since it matches the resistors
in the DAC and tracks these resistors over tempera-
ture.
Reference Voltage Input.
This input connects an external precision voltage
source to the internal DAC. The V
REF
can be selected
over the range of +25V to –25V or the analog signal for
a 4-quadrant multiplying mode application.
Power Supply Voltage.
This is the power supply pin for the part. The V
DD
can
be from +5 V DC to +15 V DC, however optimum volt-
age is +12 to +15 V DC.
BYTE1/BYTE2: Byte sequence control.
The BYTE1/BYTE2 control pin is used to select both
MSB and LSB input latches.
WR2:
XFER:
Write 2 (Active low)
It will enable XFER.
Transfer control signal (Active low)
This signal in combination with WR2 causes the 16-bit
data which is available in the input latches to transfer
to the DAC register
V
REF
:
V
DD
:
DB0 to DB11: Digital Inputs.
DB0 is the least significant digital input (LSB) and
DB11 is the most significant digital input (MSB).
I
OUT1
:
DAC Current Output 1 Bus.
I
OUT1
is a maximum for a digital code of all 1’s in the
DAC register, and is zero for all 0’s in the DAC register.
AGND: Analog Ground
Back gate of the DAC N-channel current steering
switches.
DGND: Digital Ground
Rev. 2.00
5
EXAR [ EXAR CORPORATION ]
