XRT91L33
REV. V1.0.0
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
F
IGURE
3. C
ONTROL
D
IAGRAM
F
OR
S
IGNAL
D
ETECTION
C
IRCUIT AND
PLL T
EST
O
PERATION
2
2
RXDIP/N
RXDOP/N
PLL Clock
(Internal)
0
2
RXCLKOP/N
REFCK
1
STS12_MODE
TEST
LOS (Internal)
LCKTOREFN
SIGD
2.6
Lock Detection
XRT91L33 features a PLL lock detection circuit. The lock detect (LOCK) output goes HIGH to indicate that the
PLL is locked to the serial data input and valid data and clock are present at the high-speed differential output.
The LOCK output will go LOW if either the LOCKTOREFN or the SIGD input is forced LOW. Additionally,
LOCK will also go low if the incoming data frequency is more than +/-500ppm away from the reference clock
frequency (REFCK x 32 in OC12 mode, REFCLK x 8 in OC3 mode). When LOCK output is driven LOW, the
VCO is forced to lock to REFCK and then released to lock on the incoming data. If the incoming data frequency
remains outside the +/-500ppm window, the training mode is repeated. Debounce logic stabilizes the LOCK
output pin to stay LOW for incoming frequencies well beyond the +/-500ppm window.
2.7
PLL Test Operation
The TEST pin is intended for use in production test and should be set at logic LOW in normal operation. If both
TEST and STS12_MODE pins are set to logic HIGH, XRT91L33 will bypass the PLL and present an inverted
version of the REFCK to the clock output RXCLKOP/N. REFCK’s rising edge is used to capture the input data
and transmit data to RXDOP/N. This bypass test operation can be used to facilitate board level debugging
process.
7
EXAR [ EXAR CORPORATION ]
