CMP0417AAx-E
CMOS LPRAM
LOW POWER MODES
1. Mode Register Set
A17 ~ A5
A4
A3
A2
A1
A0
Array On/Off
on /ZZ
0
1
Half Selection
Array Refresh Area
Array Refresh Area
Half Selection (Top / Bottom)
A1
0
A0
0
Type
A2
0
Type
Full Array (Default)
Bottom (Default)
Top
1)
0
1
RFU
1
1
0
½ Array
¼ Array
Array On/Off on /ZZ
A3
1
1
1. RFU : Reserved for the Future Use
Type
0
1
Partial Array Refresh Mode (Default)
Reduced Memory Size Mode
Note: The RMS(Reduced Memory Size) mode is enabled after
/ZZ goes high and remains enabled after /ZZ goes high. To
change to a different mode, the mode register will have to be
rewritten.
2. MRS Update
tWC
Address
tWR(4)
tAS(3)
tCW(2)
/CS
tAW
tBW
/UB, /LB
tWP(1)
/WE
/ZZ
tZZWE
Register Write Start
Register Write
Complete
Register Update
Complete
The register update take place on the rising edge of /ZZ. Once the register is updated, the next time /ZZ goes low, without any
updates to the register starting within the tZZWE max time of 1us, the part will refresh the array selected. The data bus is a
don’t care When /ZZ is low during the register updates.
Revision 0.5
Aug. 2006
10
FIDELIX [ FIDELIX ]
