FMP0417CAx-W70E
READ CYCLE (1)
Address
tAA
tOH
CMOS LPRAM
(Address controlled,/CS=/OE=V
IL
, /ZZ=/WE=V
IH
, /UB or/and /LB=V
IL
)
tRC
Data Out
Previous Data Valid
Data Valid
READ CYCLE (2)
Address
(/ZZ=/WE=V
IH
)
tRC
tAA
tCO
tOH
/CS
tHZ
tBA
/UB, /LB
/OE
tOLZ
tBLZ
tLZ
tBHZ
tOE
tOHZ
Data Out
High-Z
Data Valid
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
to output voltage levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device
to device interconnection.
3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us.
PAGE READ CYCLE
(/ZZ=/WE=V
IH
, 16 words access)
tMRC
tRC
tPC
tPC
tPC
tPC
tPC
tPC
tPC
A0~A3
tAA
A4~A17
tOH
tCO
/CS
tHZ
/UB, /LB
/OE
tBLZ
tBA
tBHZ
tOE
tOLZ
tPAA
tPAA
tPAA
tPAA
tPAA
tPAA
tPAA
tOHZ
Data Valid
Data Out
High-Z
tLZ
Data Valid
Data Valid
Data Valid
Data Valid
Data Valid
Data Valid
Data Valid
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
to output voltage levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device
to device interconnection.
3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us.
4. In case page address skew is over 3ns, tPAA will be out of spec.
8
Revision 0.0
Feb. 2008
FIDELIX [ FIDELIX ]
