Host Interface (HI32)
Table 1-10.
Action
Asynchronous write to host
vector
Host Port Usage Considerations (Continued)
Description
Change the Host Vector (HV) register only when the Host Command bit (HC) is clear. This practice
guarantees that the DSP interrupt control logic receives a stable vector.
1.7.2
Host Port Configuration
HI32 signal functions vary according to the programmed configuration of the interface as determined by the 24-bit
DSP Control Register (DCTR). Refer to the
DSP56301
User’s Manual
for details on HI32 configuration registers.
Table 1-11.
Signal Name
HAD[0–7]
Host Interface
Signal Description
Type
Input/Output
State During
Reset
Tri-stated
Host Address/Data 0–7
When the HI32 is programmed to interface with a PCI bus and the HI function
is selected, these signals are lines 0–7 of the Address/Data bus.
Host Address 3–10
When HI32 is programmed to interface with a universal, non-PCI bus and the
HI function is selected, these signals are lines 3–10 of the Address bus.
Port B 0–7
When the HI32 is configured as GPIO through the DCTR, these signals are
individually programmed through the HI32 Data Direction Register (DIRH).
These inputs are 5 V tolerant.
HA[3–10]
Input
PB[0–7]
Input or Output
HAD[8–15]
Input/Output
Tri-stated
Host Address/Data 8–15
When the HI32 is programmed to interface with a PCI bus and the HI function
is selected, these signals are lines 8–15 of the Address/Data bus.
Host Data 0–7
When HI32 is programmed to interface with a universal non-PCI bus and the
HI function is selected, these signals are lines 0–7 of the Data bus.
Port B 8–15
When the HI32 is configured as GPIO through the DCTR, these signals are
individually programmed through the HI32 DIRH.
These inputs are 5 V tolerant.
HD[0–7]
Input/Output
PB[8–15]
Input or Output
HC[0–3]/
HBE[0–3]
Input/Output
Tri-stated
Command 0–3/Byte Enable 0–3
When the HI32 is programmed to interface with a PCI bus and the HI function
is selected, these signals are lines 0–7 of the Address/Data bus.
Host Address 0–2
When HI32 is programmed to interface with a universal, non-PCI bus and the
HI function is selected, these signals are lines 0–2 of the Address bus.
The fourth signal in this set should connect to a pull-up resistor or directly to
V
CC
when a non-PCI bus is used.
HA[0–2]
Input
PB[16–19]
Input or Output
Port B 16–19
When the HI32 is configured as GPIO through the DCTR, these signals are
individually programmed through the HI32 DIRH.
These inputs are 5 V tolerant.
DSP56301 Technical Data, Rev. 10
Freescale Semiconductor
1-11
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
