欢迎访问ic37.com |
会员登录 免费注册
发布采购

DSP56301VF100 参数 Datasheet PDF下载

DSP56301VF100图片预览
型号: DSP56301VF100
PDF下载: 下载PDF文件 查看货源
内容描述: 24位数字信号处理器 [24-Bit Digital Signal Processor]
分类和应用: 外围集成电路数字信号处理器时钟
文件页数/大小: 124 页 / 2296 K
品牌: FREESCALE [ Freescale ]
 浏览型号DSP56301VF100的Datasheet PDF文件第13页浏览型号DSP56301VF100的Datasheet PDF文件第14页浏览型号DSP56301VF100的Datasheet PDF文件第15页浏览型号DSP56301VF100的Datasheet PDF文件第16页浏览型号DSP56301VF100的Datasheet PDF文件第18页浏览型号DSP56301VF100的Datasheet PDF文件第19页浏览型号DSP56301VF100的Datasheet PDF文件第20页浏览型号DSP56301VF100的Datasheet PDF文件第21页  
Host Interface (HI32)  
Table 1-11. Host Interface (Continued)  
State During  
Signal Name  
Type  
Signal Description  
Reset  
HPAR  
Input/  
Tri-stated  
Host Parity  
Output  
When the HI32 is programmed to interface with a PCI bus and the HI function  
is selected, this is the Host Parity signal.  
HDAK  
Input  
Host DMA Acknowledge  
When HI32 is programmed to interface with a universal, non-PCI bus and the  
HI function is selected, this is the Host DMA Acknowledge Schmitt-trigger  
signal.  
Port B  
When the HI32 is configured as GPIO through the DCTR, this signal is  
internally disconnected.  
This input is 5 V tolerant.  
HPERR  
HDRQ  
Input/  
Output  
Tri-stated  
Host Parity Error  
When the HI32 is programmed to interface with a PCI bus and the HI function  
is selected, this is the Host Parity Error signal.  
Output  
Host DMA Request  
When HI32 is programmed to interface with a universal, non-PCI bus and the  
HI function is selected, this is the Host DMA Request output.  
Port B  
When the HI32 is configured as GPIO through the DCTR, this signal is  
internally disconnected.  
This input is 5 V tolerant.  
HGNT  
HAEN  
Input  
Input  
Input  
Host Bus Grant  
When the HI32 is programmed to interface with a PCI bus and the HI function  
is selected, this is the Host Bus Grant signal.  
Host Address Enable  
When HI32 is programmed to interface with a universal, non-PCI bus and the  
HI function is selected, this is the Host Address Enable output signal.  
Port B  
When the HI32 is configured as GPIO through the DCTR, this signal is  
internally disconnected.  
This input is 5 V tolerant.  
HREQ  
HTA  
Output  
Output  
Tri-stated  
Host Bus Request  
When the HI32 is programmed to interface with a PCI bus and the HI function  
is selected, this is the Host Bus Request signal.  
Host Transfer Acknowledge—When HI32 is programmed to interface with a  
universal, non-PCI bus and the HI function is selected, this is the Host Data  
Bus Enable signal. HTA can be programmed as active high or active low.  
Port B  
When the HI32 is configured as GPIO through the DCTR, this signal is  
internally disconnected.  
This input is 5 V tolerant.  
DSP56301 Technical Data, Rev. 10  
Freescale Semiconductor  
1-13