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DSP56301VF100 参数 Datasheet PDF下载

DSP56301VF100图片预览
型号: DSP56301VF100
PDF下载: 下载PDF文件 查看货源
内容描述: 24位数字信号处理器 [24-Bit Digital Signal Processor]
分类和应用: 外围集成电路数字信号处理器时钟
文件页数/大小: 124 页 / 2296 K
品牌: FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
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Signals/Connections
1.8 Enhanced Synchronous Serial Interface 0 (ESSI0)
Two synchronous serial interfaces (ESSI0 and ESSI1) provide a full-duplex serial port for serial communication
with a variety of serial devices, including one or more industry-standard codecs, other DSPs, microprocessors, and
peripherals that implement the Serial Peripheral Interface (SPI).
Table 1-12.
Signal Name
SC00
Enhanced Synchronous Serial Interface 0 (ESSI0)
Signal Description
Serial Control 0
Functions in either Synchronous or Asynchronous mode. For Asynchronous
mode, this signal is the receive clock I/O (Schmitt-trigger input). For
Synchronous mode, this signal is either for Transmitter 1 output or Serial I/O
Flag 0.
Port C 0
The default configuration following reset is GPIO. For PC0, signal direction is
controlled through the Port Directions Register (PRR0). The signal can be
configured as ESSI signal SC00 through the Port Control Register (PCR0).
This input is 5 V tolerant.
Type
Input or Output
State During
Reset
Input
PC0
SC01
Input/Output
Input
Serial Control 1
Functions in either Synchronous or Asynchronous mode. For Asynchronous
mode, this signal is the receiver frame sync I/O. For Synchronous mode, this
signal is either Transmitter 2 output or Serial I/O Flag 1.
Port C 1
The default configuration following reset is GPIO. For PC1, signal direction is
controlled through PRR0. The signal can be configured as an ESSI signal
SC01 through PCR0.
This input is 5 V tolerant.
PC1
Input or Output
SC02
Input/Output
Input
Serial Control Signal 2
The frame sync for both the transmitter and receiver in Synchronous mode,
and for the transmitter only in Asynchronous mode. When configured as an
output, this signal is the internally generated frame sync signal. When
configured as an input, this signal receives an external frame sync signal for
the transmitter (and the receiver in synchronous operation).
Port C 2
The default configuration following reset is GPIO. For PC2, signal direction is
controlled through PRR0. The signal can be configured as an ESSI signal
SC02 through PCR0.
This input is 5 V tolerant.
PC2
Input or Output
DSP56301 Technical Data, Rev. 10
1-16
Freescale Semiconductor