Opcode Map
Table 4-1. Instruction Set Summary (Sheet 6 of 6)
Address
Mode
Opcode
Source
Form
Operation
Description
PC
←
(PC) + 1; Push (PCL)
SP
←
(SP) – 1; Push (PCH)
SP
←
(SP) – 1; Push (X)
SP
←
(SP) – 1; Push (A)
SP
←
(SP) – 1; Push (CCR)
SP
←
(SP) – 1; I
←
1
PCH
←
Interrupt Vector High Byte
PCL
←
Interrupt Vector Low Byte
CCR
←
(A)
X
←
(A)
A
←
(CCR)
V H I N Z C
SWI
Software Interrupt
– – 1 – – – INH
83
TAP
TAX
TPA
TST
opr
TSTA
TSTX
TST
opr,X
TST ,X
TST
opr,SP
TSX
TXA
TXS
WAIT
A
C
CCR
dd
dd rr
DD
DIR
DIX+
ee ff
EXT
ff
H
H
hh ll
I
ii
IMD
IMM
INH
IX
IX+
IX+D
IX1
IX1+
IX2
M
N
Transfer A to CCR
Transfer A to X
Transfer CCR to A
INH
– – – – – – INH
– – – – – – INH
DIR
INH
INH
–
IX1
IX
SP1
84
97
85
3D dd
4D
5D
6D ff
7D
9E6D ff
95
9F
94
8F
Test for Negative or Zero
(A) – $00 or (X) – $00 or (M) – $00
0 – –
Transfer SP to H:X
Transfer X to A
Transfer H:X to SP
Enable Interrupts; Wait for Interrupt
H:X
←
(SP) + 1
A
←
(X)
(SP)
←
(H:X) – 1
I bit
←
0; Inhibit CPU clocking
until interrupted
n
opr
PC
PCH
PCL
REL
rel
rr
SP1
SP2
SP
U
V
X
Z
&
|
– – – – – – INH
– – – – – – INH
– – – – – – INH
– – 0 – – – INH
Accumulator
Carry/borrow bit
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct to direct addressing mode
Direct addressing mode
Direct to indexed with post increment addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry bit
Index register high byte
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate source to direct destination addressing mode
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, no offset, post increment addressing mode
Indexed with post increment to direct addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 8-bit offset, post increment addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative bit
⊕
()
–( )
#
←
?
:
—
«
Any bit
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer, 8-bit offset addressing mode
Stack pointer 16-bit offset addressing mode
Stack pointer
Undefined
Overflow bit
Index register low byte
Zero bit
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Immediate value
Sign extend
Loaded with
If
Concatenated with
Set or cleared
Not affected
4.8 Opcode Map
See
MC68HC908JL3E Family Data Sheet, Rev. 4
Freescale Semiconductor
47
Cycles
9
2
1
1
3
1
1
3
2
4
2
1
2
1
Effect
on CCR
Operand
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
